1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the invention relates to a multistage Dickson charge pump.
2. Description of the Related Art
Recently, the decrease in the voltage applied to a gate oxide film has strongly been demanded as the gate oxide film has been thinned in accordance with a decrease in device size. Because of this demand, the logic gate power supply voltage suddenly lowers. For example, a power supply voltage of 2.5V has been used in the 0.25 μm gate length generation complementary metal oxide semiconductor (CMOS), whereas a power supply voltage of 1.2V has been used in the 70 μm gate length generation CMOS.
There is a circuit block that requires a negative voltage or a voltage higher than the logic gate power supply voltage, such as a word-line boost power supply of a dynamic random access memory (DRAM), a write power supply of an electrically erasable programmable read only memory (EEPROM), a write power supply of an anti-fuse, and a back gate power supply of a vacuum treatment (VT)-CMOS. This circuit block utilizes characteristics that are hard to benefit from the effect of device shrinkage, such as cutoff characteristics of transistors, band gap characteristics of semiconductors, and back gate characteristics thereof. The decrease in power supply voltage does not therefore advance unlike the logic gate power supply voltage described above. For example, the voltage of the word-line boost power supply voltage is 3.5V in the 0.25 μm generation DRAM, whereas it is 3.0V in the 90 nm generation DRAM. The write power supply voltage of the EEPROM is as constant as approximately 10.0V. The back gate power supply of the VT-CMOS requires a negative voltage of −1.0V or lower and a voltage that is obtained by boosting the logic gate power supply voltage by 1.0V or higher in order to benefit from the effect of an adequate reduction in cutoff current.
To achieve a high-voltage (boost-voltage) power supply or a negative-voltage power supply, a boost power supply circuit is mounted in an integrated circuit. Usually, a charge pump, which does not require any inductor that makes it difficult to save space, is often used as the boost power supply circuit mounted in the integrated circuit. The voltage of the logic gate power supply decreases and so does the supply power voltage, whereas the acquired output voltage does not decrease. The output voltage, which is twice or more as high as the supply power voltage, is often demanded. A Dickson charge pump is effective in this demand (see, for example, J. F. Dickson, “On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE J. Solid-State Circuits, June, 1976, Vol. SC-11, PP. 374-378).
As a difference between the supply power voltage and the output voltage becomes wide, the stage of a charge pump increases in number. However, the Dickson charge pump has the problem that its efficiency decreases as its stage increases (the output current decreases and the current consumption of a power supply circuit increases) (see, for example, Toru Tanzawa and Tomoharu Tanaka, “A Dynamic Analysis of the Dickson Charge Pump Circuit,” IEEE Journal of Solid-State Circuits, August, 1997, Vol. 32, No. 8, PP. 1231-1240). When an extremely high output voltage of, e.g., 10.0V is required like the voltage of the write power supply of the EEPROM and that of the write power supply of the anti-fuse, the withstand voltage of a device that configures a boost power supply circuit, especially a pumping capacitor having a large device area causes a problem.
FIG. 8 shows a configuration of a prior art Dickson charge pump. This charge pump has a four-stage configuration to allow an output voltage (boost voltage) of about 6.0V to be generated upon receipt of a supply power voltage of 2.5V.
In the prior art Dickson charge pump, five diode elements 115a to 115e are connected in series between a high-potential power supply (external power supply) 111 and an output power supply (terminal) 113. These diode elements 115a to 115e are arranged in the forward direction. One electrode of each of pumping capacitors 117a to 117d is connected to its corresponding node between a cathode terminal of one of the diode elements 115a to 115e and an anode terminal of another one of the diode elements. The pumping capacitors 117a to 117d are of the same size (capacitance c). A first clock signal Φ1 is applied to the other electrode of each of the pumping capacitors 117b and 117d, while a second clock signal Φ2 is applied to the other electrode of each of the pumping capacitors 117a and 117c. The first clock signal Φ1 is generated by a CMOS inverter circuit 119a that receives a square clock signal Φ, and the second clock signal Φ2 is generated by a CMOS inverter circuit 119b that receives the first clock signal Φ1. On the other hand, two capacitors 123a and 123b are connected in two stages (in series) between the output power supply 113 and a ground potential 121. The external power supply 111 is connected to a node between the capacitors 123a and 123b. 
FIGS. 9A to 9D illustrate an operation of the charge pump shown in FIG. 8. In order to describe the charge pump in simple language, the five diode elements 115a to 115e are compared to lock gates, and the supply power voltage of the external power supply 111, the intermediate nodes of the diode elements 115a to 115e, and the potential (output voltage) of the output power supply 113 are compared to the water levels of lock chambers partitioned by the lock gates.
FIG. 9A shows step 1 in which a first lock gate 115a′ corresponding to the first diode element 115a connected to the external power supply 111 is open. The water level of a first lock chamber 116a partitioned by the first lock gate 115a′ and a second lock gate 115b′ corresponding to the second diode element 115b becomes equal to the level of the supply power voltage (2.5V) of the external power supply 111. A third lock gate 115c′ corresponding to the third diode element 115c is also open, and the water levels of second and third lock chambers 116b and 116c are equal to each other. These water levels correspond to the intermediate potential (4.25V) between the supply power voltage (2.5V) of the external power supply and the potential (6.0V) of the output power supply 113 such that they can be imagined easily. A fifth lock gate 115e′ corresponding to the fifth (final-stage) diode element 115e connected to the output power supply 113 is open. The water level of a fourth lock chamber 116d partitioned by the fifth lock gate 115e′ and a fourth lock gate 115d′ corresponding to the fourth diode element 115d becomes equal to the level of the potential (6.0V) of the output power supply 113.
The water bottom of the second lock chamber 116b and that of the fourth lock chamber 116d are raised. This means that the potential of the first clock signal (D shown in FIG. 8 is 2.5V. The heights from the water bottoms of the lock chambers 116a to 116d to the water surfaces thereof correspond to their respective voltages applied to the pumping capacitors 117a to 117d shown in FIG. 8. More specifically, in the operating state of step 1, a voltage of 2.5V, a voltage of 1.75V, a voltage of 4.25V, and a voltage of 3.5V are applied to the first, second, third, and fourth pumping capacitors 117a, 117b, 117c, and 117d, respectively.
FIG. 9B shows step 2 that indicates the moment when the potential of the first clock signal Φ1 becomes 0V and that of the second clock signal Φ2 becomes 2.5V. For easy understanding, FIG. 9B shows a water level of each of the lock chambers 116a to 116d when all the lock gates 115a′ to 115e′ corresponding to the five diode elements 115a to 115e are closed and all the lock chambers 116a to 116d are isolated from one another. Since the charge pump shown in FIG. 8 is configured by the diode elements 115a to 115e of passive elements, the state of step 2 shifts to that of step 3 shortly.
FIG. 9C shows step 3 in which the potentials of the first and second clock signals Φ1 and Φ2 are stabilized after an adequate time elapses after the potential of the first clock signal Φ1 becomes 0V and that of the second clock signal Φ2 becomes 2.5V. The fourth lock gate 115d′ opens, and the water levels of the third and fourth lock chambers 116c and 116d become equal to each other (5.13V). The second lock gate 115b′ opens; and the water levels of the first and second lock chambers 116a and 116b become equal to each other (3.38V). The highest voltage of 5.13V is applied to the fourth lock chamber 116d, or the fourth pumping capacitor 117d. 
FIG. 9D shows step 4 in which the potential of the first clock signal Φ1 becomes 2.5V and that of the second clock signal Φ2 becomes 0V. These potentials are stabilized again in the state of step 1.
Recent integrated circuits may utilize the technology to form two different transistors that differ in thickness of oxide film on a single chip. For example, a logic gate (not shown) is configured by a transistor of a thin oxide film and its power supply voltage is decreased to about 1.2V. On the other hand, a memory device such as a DRAM and an EEPROM and an analog circuit or an input/output (I/O) circuit is configured by a transistor having a thick oxide film. The withstand voltage generated from the latter transistor is at most 2.5V to 3.3V. If a high voltage of 6.0V is directly applied to a gate oxide film, the gate oxide film is likely to be broken. To avoid this, the capacitors 123a and 123b are connected in series to the output power supply 113 as shown in FIG. 8.
The above capacitor 123a is a decoupling capacitor provided as an output load between power supplies. A decoupling capacitor is usually provided between the output power supply 113 and the ground potential 121. However, the capacitor 123a is provided between the output power supply 113 and the external power supply 111. The decoupling capacitor is generally configured by a MOS capacitor. With this configuration, the with-stand voltage of 6.0V or higher, which is originally required by the gate oxide film, can be decreased to 3.5V(=6.0V−2.5V).
The capacitor (decoupling capacitor) 123b is provided between the external power supply 111 and the ground potential 121. The output power supply 113 can tightly be coupled to the ground potential 121 through the capacitors 123a and 123b. Consequently, the noise of the output voltage is reduced and the potential is stabilized.
If the capacitor 123b between the external power supply 111 and the ground potential 121 is configured by a MOS capacitor and mounted in an integrated circuit, its coupling strength will be reduced by more than half as compared with the capacitor 123a that is directly connected to the ground potential 121. In most cases, however, the capacitance of the capacitor 123b can be compensated with an external capacitor or the parasitic capacitance of another circuit mounted in the integrated circuit. Thus, the problems that noise becomes extremely high and the area for the decoupling capacitor increases do not occur.
When the charge pump shown in FIG. 8 is so controlled that the external supply voltage is 2.5V and the output voltage is 6.0V, the highest voltage of 5.13V is applied to the final-stage pumping capacitor 117d. When the pumping capacitor is configured by a MOS capacitor, the voltage applied to the gate oxide film needs to be lowered. To do this, the final-stage pumping capacitor 117d can be configured by two MOS capacitors (capacitance c) 117d−1 and 117d−2 which are connected in series, as shown in FIG. 10.
However, the voltage at both ends of the pumping capacitor 117d increases and decreases in response to the first clock signal Φ1. It is thus difficult to compensate for the voltage of an intermediate node between the two MOS capacitors 117d−1 and 117d−2 that are connected in series. In other words, the intermediate node does not have an intermediate potential due to the influence of leakage current and parasitic capacitance and thus the effect of a decrease in the voltage applied to the gate oxide film cannot be expected. The series-connection of the MOS capacitors reduces the effective capacitance of the pumping capacitor 117d by half. Accordingly, the capability of current supply of the charge pump lowers. To compensate for this, a MOS capacitor whose area is doubled is needed. This increases not only the layout area but also the power consumption as the parasitic capacitance becomes larger.
When the final-stage pumping capacitor to which the highest voltage is applied is configured by the MOS capacitors as described above, the voltage applied to the gate oxide film needs to be lowered. A search has been made for an effective method for lowering the voltage.